In the literature, many works have proposed high-level modeling to reduce the design complexity of DPR SoCs. Therefore, the design flow proposed in this paper offers the possibility to design both centralized and decentralized control, depending on the requirements of the control problem handled by the target system. This reduces the complexity of the controllers, facilitating their verification and their reuse as well as the scalability of the control model. A coordinator that has visibility only on global system requirements and constraints can be used in this approach, leaving local control data management to the distributed controllers. Designing a decentralized control by splitting the control problem between autonomous controllers, each handling the self-adaptation of a reconfigurable component, can be beneficial for complex reconfigurable systems. In this context, it may be difficult to analyze all the control data in a centralized way. This has led to a more complex design handling different aspects related to runtime adaptation. The progress in FPGA technologies has enabled them to embed a growing number of computing resources on one chip, targeting increasingly sophisticated applications. In this context, a standard representation of the system components is required to enhance design reuse. The main issue of the deployment phase of most MDE methodologies in the literature is that the deployed hardware IPs are tightly linked to the implementation technology, which makes both high-level models and actual IPs hardly reusable for various technologies. This can be the case with the reconfiguration controller, for instance. Furthermore, the code of some high-level components, with non-existent implementing IPs, can be generated from the UML descriptions of their behaviors, such as UML state machines. All the necessary code for IP communication and system implementation is then generated automatically from high-level models. To allow this feature, MDE approaches often use a deployment phase that links the components of high-level models to low-level implementations through IPs (Intellectual Properties). One of the advantages of using MDE is that it allows for generating a system implementation code from high-level models. This hardware efficiency was achieved in a very short time thanks to the design acceleration and automation offered by model-driven engineering. Experimental results showed that the generated system allowed a good trade-off between resource usage, power consumption, execution time, and image quality compared to static implementations. The proposed design flow was validated through a reconfigurable video watermarking application as a case study. At the end of the flow, the implementation code is generated automatically from the high-level models. It also integrates the IP-XACT standard (standard for the description of electronic Intellectual Properties), allowing the designer to easily target different technologies and commercial FPGAs by reusing both high-level models and actual IP-XACT hardware components. Both centralized and decentralized reconfiguration decision-making solutions are possible with the proposed flow, allowing it to adapt to various reconfigurable systems constraints. It is based on high-level modeling using an extended version of the MARTE (Modeling and Analysis of Real-Time and Embedded systems) UML (Unified Modeling Language) profile. To address this issue, this paper proposes a model-driven design flow that guides the designer through the description of the different elements of a reconfigurable system. However, this implies additional design tasks to handle system reconfiguration and control, which increases design complexity. The reconfigurable feature of FPGAs (Field-Programmable Gate Arrays) has made them a very attractive solution for implementing adaptive systems-on-chip.
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